Software Engineer Intern - Compilers

You will be a member of the TIE compiler (TC) team at the Compute System Group (CSG) of Cadence. Tensilica Instruction Extension (TIE) is a proprietary language that allows customers to extend the Tensilica processors with custom instructions, coprocessors and hardware accelerators, allowing them to increase application specific performance and efficiency by orders of magnitude, while maintaining ease of programmability through a fully generated tool-chain. The TIE compiler translates TIE into efficient Verilog HDL implementation and generates libraries used by the software tool chain.instructions, coprocessors and hardware accelerators, allowing them to increase application specific performance and efficiency by orders of magnitude, while maintaining ease of programmability through a fully generated tool-chain. The TIE compiler translates TIE into efficient Verilog HDL implementation and generates libraries used by the software tool chain.

Fine tune open source LLM to design TIE codepilot (to generate new Instruction description in TIE language from natural language description)